Abstract
Cryptographic hash functions are used to protect information integrity and authenticity in a wide range of applications. After the discovery of weaknesses in the current deployed standards, the U.S. Institute of Standards and Technology started a public competition to develop the future standard SHA-3, which will be implemented in a multitude of environments, after its selection in 2012. In this paper, we investigate high-speed and low-area hardware architectures of one of the 14 second-round candidates in this competition: BLAKE. VLSI performance results of the proposed high-speed designs indicate a throughput improvement between 16% and 36% compared to the current standard SHA-2. Additionally, we propose a compact implementation of BLAKE with memory optimization that fits in 0.127 mm 2 of a 0.18 μm CMOS. Measurements reveal a minimal power dissipation of 9.59 μW/MHz at 0.65 V, which suggests that BLAKE is suitable for resource-limited systems.
Original language | English |
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Article number | 5551268 |
Pages (from-to) | 1746-1754 |
Number of pages | 9 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 19 |
Issue number | 10 |
DOIs | |
Publication status | Published - Oct 2011 |
Externally published | Yes |
Keywords
- Cryptographic hash functions
- latch memory
- low-power
- SHA-3
- VLSI implementations