Stress induced damages in SiOC and porous SiOC single Via Kelvin structures investigation methodology, failure description and improved via barrier approaches

A. Fuchsmann, V. Arnal, W. Besling, Y. Brechet, M. Verdier, J. Torres

Research output: Chapter in Book/Report/Conference proceedingConference PaperOther


Stress induced voiding experiments were carried out at 225°C for 960hrs on full wafer samples using Via Kelvin structures. The samples used CVD SiOC low k (k=2.9) and porous CVD SiOC low k (k=2.2) as dielectric materials and several TaN diffusion barriers, including physical vapour deposited (PVD) TaN-Ta, atomic layer deposited (ALD) TaN and self ionized plasma deposited (SIP) TaN-Ta Punch-Through barriers. Via resistances were measured and analyzed to follow their evolution and failed via structures were identified on the basis of a 10% resistance shift. The as obtained data were used to compare the SIV behaviour of the different samples, leading to the conclusion that samples with ALD and Punch-Through approaches demonstrate improved SIV behaviour with twice less SIV affected structures.

Original languageEnglish
Title of host publicationAdvanced Metallization Conference 2004
Number of pages5
Publication statusPublished - 2004
Externally publishedYes
EventAdvanced Metallization Conference 2004 - San Diego, United States of America
Duration: 19 Oct 200421 Oct 2004

Publication series

NameAdvanced Metallization Conference (AMC)
ISSN (Print)1540-1766


ConferenceAdvanced Metallization Conference 2004
Abbreviated titleAMC 2004
CountryUnited States of America
CitySan Diego

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