Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will adapt random delays at runtime due to time borrowing. The central problem to determine the timing yield is to compute the probability of the presence of a positive cycle in the latest latch timing graph. Existing algorithms are either optimistic since cycles are omitted or require iterations that cannot be polynomially bounded. In this paper, we present the first algorithm to compute such probability based on block-based statistical timing analysis that, first, covers all cycles through a structural graph traversal, and second, terminates within a polynomial number of statistical "sum" and "max" operations. Experimental results confirm that the proposed approach is effective and efficient.
|Title of host publication||2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010|
|Number of pages||6|
|Publication status||Published - 28 Apr 2010|
|Event||2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan|
Duration: 18 Jan 2010 → 21 Jan 2010
|Conference||2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010|
|Period||18/01/10 → 21/01/10|