TY - JOUR
T1 - Secure integrated circuit design via hybrid cloud
AU - Yuan, Xingliang
AU - Weng, Jian
AU - Wang, Cong
AU - Ren, Kui
PY - 2018/8
Y1 - 2018/8
N2 - In order to ease the burden of the in-house integrated circuit (IC) design, cloud-based IC design platforms advance rapidly, bringing benefits such as reduced capital costs and convenient design collaboration. However, such migration raises security challenges on IC Intellectual Property (IP) protection. Sensitive design data is unwillingly exposed to the cloud. In this paper, we initiate the first study for secure cloud-based IC design, and propose a hybrid cloud framework for privacy-assured IC timing analysis, i.e., an expensive procedure in the IC design flow for circuit delay evaluation. Our key observation is that more and more IP blocks are universally reused. After carefully extracting a small portion of sensitive blocks from the circuit, our framework only outsources non-sensitive design data to the public cloud. However, that 'data splitting' hinders sequential delay evaluation. We then develop algorithms to enable the public cloud to derive intermediate results from non-sensitive data, which can be integrated with sensitive data at the private cloud. Additionally, we devise a practical verification protocol to assure the integrity of outsourced computation. Security analysis shows that our design is resilient to IC reverse engineering. Evaluations over large IC benchmarks demonstrate its efficiency and effectiveness.
AB - In order to ease the burden of the in-house integrated circuit (IC) design, cloud-based IC design platforms advance rapidly, bringing benefits such as reduced capital costs and convenient design collaboration. However, such migration raises security challenges on IC Intellectual Property (IP) protection. Sensitive design data is unwillingly exposed to the cloud. In this paper, we initiate the first study for secure cloud-based IC design, and propose a hybrid cloud framework for privacy-assured IC timing analysis, i.e., an expensive procedure in the IC design flow for circuit delay evaluation. Our key observation is that more and more IP blocks are universally reused. After carefully extracting a small portion of sensitive blocks from the circuit, our framework only outsources non-sensitive design data to the public cloud. However, that 'data splitting' hinders sequential delay evaluation. We then develop algorithms to enable the public cloud to derive intermediate results from non-sensitive data, which can be integrated with sensitive data at the private cloud. Additionally, we devise a practical verification protocol to assure the integrity of outsourced computation. Security analysis shows that our design is resilient to IC reverse engineering. Evaluations over large IC benchmarks demonstrate its efficiency and effectiveness.
KW - computation outsourcing
KW - Hybrid cloud
KW - IP protection
UR - http://www.scopus.com/inward/record.url?scp=85042369345&partnerID=8YFLogxK
U2 - 10.1109/TPDS.2018.2807844
DO - 10.1109/TPDS.2018.2807844
M3 - Article
AN - SCOPUS:85042369345
VL - 29
SP - 1851
EP - 1864
JO - IEEE Transactions on Parallel and Distributed Systems
JF - IEEE Transactions on Parallel and Distributed Systems
SN - 1045-9219
IS - 8
ER -