Non-volatile D-latch for sequential logic circuits using memristors

Patrick W.C. Ho; Haider Abbas F. Almurib; T. Nandha Kumar

doi:10.1109/TENCON.2015.7372849

Non-volatile D-latch for sequential logic circuits using memristors

Patrick W.C. Ho, Haider Abbas F. Almurib, T. Nandha Kumar

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Research › peer-review

4 Citations (Scopus)

Abstract

This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL is more energy efficient than the CMOS based volatile D-latch. The energy required by NVDL to store or retrieve the data is 1.5 times lesser than the CMOS based D-latch. In addition, the NVDL switching speed is increased by 1.54 times when compared with previous NV latches design.

Original language	English
Title of host publication	TENCON 2015 - 2015 IEEE Region 10 Conference
Publisher	IEEE, Institute of Electrical and Electronics Engineers
ISBN (Electronic)	9781479986415
DOIs	https://doi.org/10.1109/TENCON.2015.7372849
Publication status	Published - 2015
Externally published	Yes
Event	IEEE Tencon (IEEE Region 10 Conference) 2015 - Holiday Inn Sands Cotai Central, Macau, China Duration: 1 Nov 2015 → 4 Nov 2015 Conference number: 35th https://ieeexplore.ieee.org/xpl/conhome/7365563/proceeding (Proceedings) http://www.ieeer10.org/meeting/Macau%20Section%20-%20TENCON%202015.pdf

Publication series

Name	IEEE Region 10 Annual International Conference, Proceedings/TENCON
Volume	2016-January
ISSN (Print)	2159-3442
ISSN (Electronic)	2159-3450

Conference

Conference	IEEE Tencon (IEEE Region 10 Conference) 2015
Abbreviated title	TENCON 2015
Country/Territory	China
City	Macau
Period	1/11/15 → 4/11/15
Internet address	https://ieeexplore.ieee.org/xpl/conhome/7365563/proceeding (Proceedings) http://www.ieeer10.org/meeting/Macau%20Section%20-%20TENCON%202015.pdf

Keywords

latch
memristor
Sequential logic circuit

Access to Document

10.1109/TENCON.2015.7372849

Cite this

Ho, P. W. C., Almurib, H. A. F., & Kumar, T. N. (2015). Non-volatile D-latch for sequential logic circuits using memristors. In TENCON 2015 - 2015 IEEE Region 10 Conference Article 7372849 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2016-January). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/TENCON.2015.7372849

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title = "Non-volatile D-latch for sequential logic circuits using memristors",

abstract = "This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL is more energy efficient than the CMOS based volatile D-latch. The energy required by NVDL to store or retrieve the data is 1.5 times lesser than the CMOS based D-latch. In addition, the NVDL switching speed is increased by 1.54 times when compared with previous NV latches design.",

keywords = "latch, memristor, Sequential logic circuit",

author = "Ho, {Patrick W.C.} and Almurib, {Haider Abbas F.} and Kumar, {T. Nandha}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; IEEE Tencon (IEEE Region 10 Conference) 2015, TENCON 2015 ; Conference date: 01-11-2015 Through 04-11-2015",

year = "2015",

doi = "10.1109/TENCON.2015.7372849",

language = "English",

series = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

booktitle = "TENCON 2015 - 2015 IEEE Region 10 Conference",

address = "United States of America",

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Ho, PWC, Almurib, HAF & Kumar, TN 2015, Non-volatile D-latch for sequential logic circuits using memristors. in TENCON 2015 - 2015 IEEE Region 10 Conference., 7372849, IEEE Region 10 Annual International Conference, Proceedings/TENCON, vol. 2016-January, IEEE, Institute of Electrical and Electronics Engineers, IEEE Tencon (IEEE Region 10 Conference) 2015, Macau, China, 1/11/15. https://doi.org/10.1109/TENCON.2015.7372849

Non-volatile D-latch for sequential logic circuits using memristors. / Ho, Patrick W.C.; Almurib, Haider Abbas F.; Kumar, T. Nandha.
TENCON 2015 - 2015 IEEE Region 10 Conference. IEEE, Institute of Electrical and Electronics Engineers, 2015. 7372849 (IEEE Region 10 Annual International Conference, Proceedings/TENCON; Vol. 2016-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Research › peer-review

TY - GEN

T1 - Non-volatile D-latch for sequential logic circuits using memristors

AU - Ho, Patrick W.C.

AU - Almurib, Haider Abbas F.

AU - Kumar, T. Nandha

N1 - Conference code: 35th

PY - 2015

Y1 - 2015

N2 - This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL is more energy efficient than the CMOS based volatile D-latch. The energy required by NVDL to store or retrieve the data is 1.5 times lesser than the CMOS based D-latch. In addition, the NVDL switching speed is increased by 1.54 times when compared with previous NV latches design.

AB - This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL is more energy efficient than the CMOS based volatile D-latch. The energy required by NVDL to store or retrieve the data is 1.5 times lesser than the CMOS based D-latch. In addition, the NVDL switching speed is increased by 1.54 times when compared with previous NV latches design.

KW - latch

KW - memristor

KW - Sequential logic circuit

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BT - TENCON 2015 - 2015 IEEE Region 10 Conference

PB - IEEE, Institute of Electrical and Electronics Engineers

T2 - IEEE Tencon (IEEE Region 10 Conference) 2015

Y2 - 1 November 2015 through 4 November 2015

ER -

Non-volatile D-latch for sequential logic circuits using memristors

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