Multistage linear feedback shift register counters with reduced decoding logic in 130-nm CMOS for large-scale array applications

Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean Michel Redoute

Research output: Contribution to journalArticleResearchpeer-review

Abstract

Linear-feedback shift register (LFSR) counters have been shown to be well suited to applications requiring large arrays of counters and can improve the area and performance compared with conventional binary counters. However, significant logic is required to decode the count order into binary, causing system-on-chip designs to be unfeasible. This paper presents a counter design based on multiple LFSR stages that retains the advantages of a single-stage LFSR but only requires decoding logic that scales logarithmically with the number of stages rather than exponentially with the number of bits as required by other methods. A four-stage four-bit LFSR proof of concept was fabricated in 130-nm CMOS and was characterized in a time-to-digital converter application at 800 MHz.

Original languageEnglish
Pages (from-to)103-115
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number1
DOIs
Publication statusPublished - 1 Jan 2019

Keywords

  • 3-D imaging
  • binary counters
  • decoding logic
  • event counters
  • linear-feedback shift register (LFSR)
  • single-photon detection.

Cite this

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title = "Multistage linear feedback shift register counters with reduced decoding logic in 130-nm CMOS for large-scale array applications",
abstract = "Linear-feedback shift register (LFSR) counters have been shown to be well suited to applications requiring large arrays of counters and can improve the area and performance compared with conventional binary counters. However, significant logic is required to decode the count order into binary, causing system-on-chip designs to be unfeasible. This paper presents a counter design based on multiple LFSR stages that retains the advantages of a single-stage LFSR but only requires decoding logic that scales logarithmically with the number of stages rather than exponentially with the number of bits as required by other methods. A four-stage four-bit LFSR proof of concept was fabricated in 130-nm CMOS and was characterized in a time-to-digital converter application at 800 MHz.",
keywords = "3-D imaging, binary counters, decoding logic, event counters, linear-feedback shift register (LFSR), single-photon detection.",
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Multistage linear feedback shift register counters with reduced decoding logic in 130-nm CMOS for large-scale array applications. / Morrison, Daniel; Delic, Dennis; Yuce, Mehmet Rasit; Redoute, Jean Michel.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, 01.01.2019, p. 103-115.

Research output: Contribution to journalArticleResearchpeer-review

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