High-performance logic and memory devices based on a dual-gated MoS2 architecture

Fuyou Liao, Zhongxun Guo, Yin Wang, Yufeng Xie, Simeng Zhang, Yaochen Sheng, Hongwei Tang, Zihan Xu, Antoine Riaud, Peng Zhou, Jing Wan, Michael S. Fuhrer, Xiangwei Jiang, David Wei Zhang, Yang Chai, Wenzhong Bao

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30 Citations (Scopus)


We demonstrate dual-gated (DG) MoS2 field effect transistors (FETs) in which the degraded switching performance of multilayer MoS2 can be compensated by the DG structure. It produces large current density (>100 μA/μm for a monolayer), steep subthreshold swing (SS) (∼100 mV/dec for 5 nm thickness), and high on/off current ratio (>107 for 10 nm thickness). Such DG structure not only improves electrostatic control but also provides an extra degree of freedom for manipulating the threshold voltage (VTH) and SS by separately tuning the top and back gate voltages, which are demonstrated in a logic inverter. Dynamic random access memory (DRAM) has a short retention time because of large OFF-state current in the Si MOSFET. Based on our DG MoS2-FETs, a DRAM unit cell with a long retention time of 1260 ms is realized. Large-scale isolated MoS2 DG-FETs based on CVD-synthesized continuous films are also demonstrated, which show potential applications for future wafer-scale digital and low-power electronics.

Original languageEnglish
Pages (from-to)111-119
Number of pages9
JournalACS Applied Electronic Materials
Issue number1
Publication statusPublished - 28 Jan 2020


  • Dual-gate
  • Dynamic random access memory cells
  • Field-effect transistors
  • Inverters
  • MoS

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