Hardware-in-the-loop validation of an FPGA-based real-time simulator for power electronics applications

Reza Razzaghi, Frédéric Colas, Xavier Guillaud, Mario Paolone, Farhad Rachidi

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearchpeer-review

Abstract

This paper presents the hardware-in-the-loop (HIL) validation of a proposed FPGA-based real-time simulator for power electronics applications. The proposed FPGA-based real-time simulation platform integrates the Modified Nodal Analysis (MNA) method, Fixed Admittance Matrix Nodal Method (FAMNM) and an optimization technique to assess the optimal value of the switches conductance in order to minimize the relevant errors. Moreover, the proposed platform includes an automatic procedure to translate the netlist user-defined circuit schemes to the relevant equations to be solved in the FPGA. The proposed simulator is validated first by comparing the FPGA- based simulation results with
offline ones performed by EMTP- RV. Then, further validation is presented by means of a dedicated HIL experimental setup composed of a controller connected to an actual two-level, three-phase inverter and its corresponding FPGA real-time model.
Original languageEnglish
Title of host publicationProceedings of the 11th International Conference on Power Systems Transients (IPST)
Subtitle of host publicationCavtat, Croatia: June 15-18, 2015
EditorsT. Funabashi, M.C. Tavares
Place of PublicationCavtat Croatia
PublisherIPST
Number of pages7
Publication statusPublished - 2015
Externally publishedYes
EventInternational Conference on Power Systems Transients 2015 - Cavtat, Croatia
Duration: 15 Jun 201518 Jun 2015

Conference

ConferenceInternational Conference on Power Systems Transients 2015
Country/TerritoryCroatia
CityCavtat
Period15/06/1518/06/15

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