FPGA acceleration of multilevel ORB feature extraction for computer vision

Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearchpeer-review

5 Citations (Scopus)

Abstract

In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. The design has been validated both in behavioural simulation and in implementation on an Arria V FPGA connected to a desktop PC via PCI-Express. A Linux kernel-mode driver and userspace library allow integration of the acceleration hardware into C++ programs. The device has significantly higher throughput than a CPU implementation (150 MPixel/s vs 27 MPixel/s) and a GPU implementation (40 MPixel/s), with much lower power draw (5.3 W vs 145 W). This throughput is equivalent to 72 fps at 1920 × 1080 or 488 fps at 640 × 480.

Original languageEnglish
Title of host publication2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017)
EditorsMarco Santambrogio, Diana Göhringer
Place of PublicationReston VA USA
PublisherIEEE, Institute of Electrical and Electronics Engineers
Number of pages8
ISBN (Electronic)9789090304281
DOIs
Publication statusPublished - 2 Oct 2017
EventInternational Conference on Field Programmable Logic and Applications 2017
- Gent, Belgium
Duration: 4 Sep 20176 Sep 2017
Conference number: 27th

Conference

ConferenceInternational Conference on Field Programmable Logic and Applications 2017
Abbreviated titleFPL 2017
CountryBelgium
CityGent
Period4/09/176/09/17

Cite this

Weberruss, J., Kleeman, L., Boland, D., & Drummond, T. (2017). FPGA acceleration of multilevel ORB feature extraction for computer vision. In M. Santambrogio, & D. Göhringer (Eds.), 2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017) [8056856] Reston VA USA: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.23919/FPL.2017.8056856
Weberruss, Josh ; Kleeman, Lindsay ; Boland, David ; Drummond, Tom. / FPGA acceleration of multilevel ORB feature extraction for computer vision. 2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017). editor / Marco Santambrogio ; Diana Göhringer. Reston VA USA : IEEE, Institute of Electrical and Electronics Engineers, 2017.
@inproceedings{d8a82921d242467981db21af57df6de6,
title = "FPGA acceleration of multilevel ORB feature extraction for computer vision",
abstract = "In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. The design has been validated both in behavioural simulation and in implementation on an Arria V FPGA connected to a desktop PC via PCI-Express. A Linux kernel-mode driver and userspace library allow integration of the acceleration hardware into C++ programs. The device has significantly higher throughput than a CPU implementation (150 MPixel/s vs 27 MPixel/s) and a GPU implementation (40 MPixel/s), with much lower power draw (5.3 W vs 145 W). This throughput is equivalent to 72 fps at 1920 × 1080 or 488 fps at 640 × 480.",
author = "Josh Weberruss and Lindsay Kleeman and David Boland and Tom Drummond",
year = "2017",
month = "10",
day = "2",
doi = "10.23919/FPL.2017.8056856",
language = "English",
editor = "Santambrogio, {Marco } and G{\"o}hringer, {Diana }",
booktitle = "2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017)",
publisher = "IEEE, Institute of Electrical and Electronics Engineers",
address = "United States of America",

}

Weberruss, J, Kleeman, L, Boland, D & Drummond, T 2017, FPGA acceleration of multilevel ORB feature extraction for computer vision. in M Santambrogio & D Göhringer (eds), 2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017)., 8056856, IEEE, Institute of Electrical and Electronics Engineers, Reston VA USA, International Conference on Field Programmable Logic and Applications 2017
, Gent, Belgium, 4/09/17. https://doi.org/10.23919/FPL.2017.8056856

FPGA acceleration of multilevel ORB feature extraction for computer vision. / Weberruss, Josh; Kleeman, Lindsay; Boland, David; Drummond, Tom.

2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017). ed. / Marco Santambrogio; Diana Göhringer. Reston VA USA : IEEE, Institute of Electrical and Electronics Engineers, 2017. 8056856.

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearchpeer-review

TY - GEN

T1 - FPGA acceleration of multilevel ORB feature extraction for computer vision

AU - Weberruss, Josh

AU - Kleeman, Lindsay

AU - Boland, David

AU - Drummond, Tom

PY - 2017/10/2

Y1 - 2017/10/2

N2 - In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. The design has been validated both in behavioural simulation and in implementation on an Arria V FPGA connected to a desktop PC via PCI-Express. A Linux kernel-mode driver and userspace library allow integration of the acceleration hardware into C++ programs. The device has significantly higher throughput than a CPU implementation (150 MPixel/s vs 27 MPixel/s) and a GPU implementation (40 MPixel/s), with much lower power draw (5.3 W vs 145 W). This throughput is equivalent to 72 fps at 1920 × 1080 or 488 fps at 640 × 480.

AB - In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. The design has been validated both in behavioural simulation and in implementation on an Arria V FPGA connected to a desktop PC via PCI-Express. A Linux kernel-mode driver and userspace library allow integration of the acceleration hardware into C++ programs. The device has significantly higher throughput than a CPU implementation (150 MPixel/s vs 27 MPixel/s) and a GPU implementation (40 MPixel/s), with much lower power draw (5.3 W vs 145 W). This throughput is equivalent to 72 fps at 1920 × 1080 or 488 fps at 640 × 480.

UR - http://www.scopus.com/inward/record.url?scp=85034451609&partnerID=8YFLogxK

U2 - 10.23919/FPL.2017.8056856

DO - 10.23919/FPL.2017.8056856

M3 - Conference Paper

AN - SCOPUS:85034451609

BT - 2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017)

A2 - Santambrogio, Marco

A2 - Göhringer, Diana

PB - IEEE, Institute of Electrical and Electronics Engineers

CY - Reston VA USA

ER -

Weberruss J, Kleeman L, Boland D, Drummond T. FPGA acceleration of multilevel ORB feature extraction for computer vision. In Santambrogio M, Göhringer D, editors, 2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017). Reston VA USA: IEEE, Institute of Electrical and Electronics Engineers. 2017. 8056856 https://doi.org/10.23919/FPL.2017.8056856