FPGA acceleration of multilevel ORB feature extraction for computer vision

Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearchpeer-review

11 Citations (Scopus)

Abstract

In this paper, we present the first multilevel implementation of the Harris-Stephens corner detector and the ORB feature extractor running on FPGA hardware, for computer vision and robotics applications. ORB is a fundamental component of many robotics applications, and requires significant computation. The design has been validated both in behavioural simulation and in implementation on an Arria V FPGA connected to a desktop PC via PCI-Express. A Linux kernel-mode driver and userspace library allow integration of the acceleration hardware into C++ programs. The device has significantly higher throughput than a CPU implementation (150 MPixel/s vs 27 MPixel/s) and a GPU implementation (40 MPixel/s), with much lower power draw (5.3 W vs 145 W). This throughput is equivalent to 72 fps at 1920 × 1080 or 488 fps at 640 × 480.

Original languageEnglish
Title of host publication2017 27th International Conference on Field Programmable Logic and Applications (FPL 2017)
EditorsMarco Santambrogio, Diana Göhringer
Place of PublicationReston VA USA
PublisherIEEE, Institute of Electrical and Electronics Engineers
Number of pages8
ISBN (Electronic)9789090304281
DOIs
Publication statusPublished - 2 Oct 2017
EventInternational Conference on Field Programmable Logic and Applications 2017
- Gent, Belgium
Duration: 4 Sep 20176 Sep 2017
Conference number: 27th

Conference

ConferenceInternational Conference on Field Programmable Logic and Applications 2017
Abbreviated titleFPL 2017
CountryBelgium
CityGent
Period4/09/176/09/17

Cite this