Fast implementation of the phase shift beamformer

Grant Hampson; Andrew Paplinski

Fast implementation of the phase shift beamformer

Grant Hampson, Andrew Paplinski

Department of Data Science & AI

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

This paper describes a combined standard-cell/FPGA implementation of a Phase Shift Beamformer. To obtain high-resolution real-time images a word-parallel pipelined CORDIC processor is used to compute the large number of complex multiplications needed. Analogue pre-processing amplifies, demodulates and samples outputs from a 16 sensor linear ultrasonic array. The current system is configured to form 2-d images, however using additional CORDIC processors a 3-d beamformer can be realised.

Original language	English
Pages	27-30
Number of pages	4
Publication status	Published - 1 Dec 1996
Event	Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology - Boston, United States of America Duration: 15 Oct 1996 → 18 Oct 1996

Conference

Conference	Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology
Country/Territory	United States of America
City	Boston
Period	15/10/96 → 18/10/96

Cite this

@conference{a32c6fcf790f4fa7b82074321fbadcf3,

title = "Fast implementation of the phase shift beamformer",

abstract = "This paper describes a combined standard-cell/FPGA implementation of a Phase Shift Beamformer. To obtain high-resolution real-time images a word-parallel pipelined CORDIC processor is used to compute the large number of complex multiplications needed. Analogue pre-processing amplifies, demodulates and samples outputs from a 16 sensor linear ultrasonic array. The current system is configured to form 2-d images, however using additional CORDIC processors a 3-d beamformer can be realised.",

author = "Grant Hampson and Andrew Paplinski",

year = "1996",

month = dec,

day = "1",

language = "English",

pages = "27--30",

note = "Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology ; Conference date: 15-10-1996 Through 18-10-1996",

}

TY - CONF

T1 - Fast implementation of the phase shift beamformer

AU - Hampson, Grant

AU - Paplinski, Andrew

PY - 1996/12/1

Y1 - 1996/12/1

N2 - This paper describes a combined standard-cell/FPGA implementation of a Phase Shift Beamformer. To obtain high-resolution real-time images a word-parallel pipelined CORDIC processor is used to compute the large number of complex multiplications needed. Analogue pre-processing amplifies, demodulates and samples outputs from a 16 sensor linear ultrasonic array. The current system is configured to form 2-d images, however using additional CORDIC processors a 3-d beamformer can be realised.

AB - This paper describes a combined standard-cell/FPGA implementation of a Phase Shift Beamformer. To obtain high-resolution real-time images a word-parallel pipelined CORDIC processor is used to compute the large number of complex multiplications needed. Analogue pre-processing amplifies, demodulates and samples outputs from a 16 sensor linear ultrasonic array. The current system is configured to form 2-d images, however using additional CORDIC processors a 3-d beamformer can be realised.

UR - http://www.scopus.com/inward/record.url?scp=0030407838&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0030407838

SP - 27

EP - 30

T2 - Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology

Y2 - 15 October 1996 through 18 October 1996

ER -

Fast implementation of the phase shift beamformer

Abstract

Conference

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Cite this