Fast implementation of the phase shift beamformer

Grant Hampson, Andrew Paplinski

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

This paper describes a combined standard-cell/FPGA implementation of a Phase Shift Beamformer. To obtain high-resolution real-time images a word-parallel pipelined CORDIC processor is used to compute the large number of complex multiplications needed. Analogue pre-processing amplifies, demodulates and samples outputs from a 16 sensor linear ultrasonic array. The current system is configured to form 2-d images, however using additional CORDIC processors a 3-d beamformer can be realised.

Original languageEnglish
Pages27-30
Number of pages4
Publication statusPublished - 1 Dec 1996
EventProceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology - Boston, United States of America
Duration: 15 Oct 199618 Oct 1996

Conference

ConferenceProceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology
CountryUnited States of America
CityBoston
Period15/10/9618/10/96

Cite this

Hampson, G., & Paplinski, A. (1996). Fast implementation of the phase shift beamformer. 27-30. Paper presented at Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology, Boston, United States of America.