This paper describes a combined standard-cell/FPGA implementation of a Phase Shift Beamformer. To obtain high-resolution real-time images a word-parallel pipelined CORDIC processor is used to compute the large number of complex multiplications needed. Analogue pre-processing amplifies, demodulates and samples outputs from a 16 sensor linear ultrasonic array. The current system is configured to form 2-d images, however using additional CORDIC processors a 3-d beamformer can be realised.
|Number of pages||4|
|Publication status||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology - Boston, United States of America|
Duration: 15 Oct 1996 → 18 Oct 1996
|Conference||Proceedings of the 1996 IEEE International Symposium on Phased Array Systems and Technology|
|Country||United States of America|
|Period||15/10/96 → 18/10/96|