Design and synthesis of reversible arithmetic and Logic Unit (ALU)

Lenin Gopal; Nor Syahira Mohd Mahayadin; Adib Kabir Chowdhury; Alpha Agape Gopalai; Ashutosh Kumar Singh

doi:10.1109/I4CT.2014.6914191

Design and synthesis of reversible arithmetic and Logic Unit (ALU)

Lenin Gopal, Nor Syahira Mohd Mahayadin, Adib Kabir Chowdhury, Alpha Agape Gopalai, Ashutosh Kumar Singh

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Other

36 Citations (Scopus)

Abstract

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Original language	English
Title of host publication	I4CT 2014 - 1st International Conference on Computer, Communications, and Control Technology, Proceedings
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	289-293
Number of pages	5
ISBN (Electronic)	9781479945559
DOIs	https://doi.org/10.1109/I4CT.2014.6914191
Publication status	Published - 30 Sept 2014
Externally published	Yes
Event	International Conference on Computer, Communications, and Control Technology 2014 - Langkawi, Kedah, Malaysia Duration: 2 Sept 2014 → 4 Sept 2014 Conference number: 1st https://ieeexplore.ieee.org/xpl/conhome/6902668/proceeding (Proceedings)

Conference

Conference	International Conference on Computer, Communications, and Control Technology 2014
Abbreviated title	I4CT 2014
Country/Territory	Malaysia
City	Langkawi, Kedah
Period	2/09/14 → 4/09/14
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6902668/proceeding (Proceedings)

Keywords

propagation delay
reversible ALU design
reversible full adder

Access to Document

10.1109/I4CT.2014.6914191

Cite this

Gopal, L., Mohd Mahayadin, N. S., Chowdhury, A. K., Gopalai, A. A., & Singh, A. K. (2014). Design and synthesis of reversible arithmetic and Logic Unit (ALU). In I4CT 2014 - 1st International Conference on Computer, Communications, and Control Technology, Proceedings (pp. 289-293). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/I4CT.2014.6914191

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title = "Design and synthesis of reversible arithmetic and Logic Unit (ALU)",

abstract = "In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.",

keywords = "propagation delay, reversible ALU design, reversible full adder",

author = "Lenin Gopal and {Mohd Mahayadin}, {Nor Syahira} and Chowdhury, {Adib Kabir} and Gopalai, {Alpha Agape} and Singh, {Ashutosh Kumar}",

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Gopal, L, Mohd Mahayadin, NS, Chowdhury, AK, Gopalai, AA & Singh, AK 2014, Design and synthesis of reversible arithmetic and Logic Unit (ALU). in I4CT 2014 - 1st International Conference on Computer, Communications, and Control Technology, Proceedings. IEEE, Institute of Electrical and Electronics Engineers, pp. 289-293, International Conference on Computer, Communications, and Control Technology 2014, Langkawi, Kedah, Malaysia, 2/09/14. https://doi.org/10.1109/I4CT.2014.6914191

Design and synthesis of reversible arithmetic and Logic Unit (ALU). / Gopal, Lenin; Mohd Mahayadin, Nor Syahira; Chowdhury, Adib Kabir et al.
I4CT 2014 - 1st International Conference on Computer, Communications, and Control Technology, Proceedings. IEEE, Institute of Electrical and Electronics Engineers, 2014. p. 289-293.

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Other

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AU - Mohd Mahayadin, Nor Syahira

AU - Chowdhury, Adib Kabir

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AU - Singh, Ashutosh Kumar

N1 - Conference code: 1st

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N2 - In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

AB - In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

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Design and synthesis of reversible arithmetic and Logic Unit (ALU)

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Keywords

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