Configurable memristive logic block for memristive-based FPGA architectures

Patrick W.C. Ho, Haider Abbas F. Almurib, T. Nandha Kumar, Haider Abbas F. Almurib

Research output: Contribution to journalArticleResearchpeer-review

11 Citations (Scopus)


This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25 nW, and the memristive logic cells reduce device area by 60.416 µm2. In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture.

Original languageEnglish
Pages (from-to)61-69
Number of pages9
Publication statusPublished - Jan 2017
Externally publishedYes


  • Configurable logic block
  • FPGA Architecture
  • Logic block
  • Memristor
  • Switch block

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