An efficient successive cancellation polar decoder based on new folding approaches

Xiao Liang; Yechao She; Harish Vangala; Xiaohu You; Chuan Zhang; Emanuele Viterbo

doi:10.1109/ASICON.2017.8252666

An efficient successive cancellation polar decoder based on new folding approaches

Xiao Liang
, Yechao She
, Harish Vangala
, Xiaohu You
, Chuan Zhang
, Emanuele Viterbo

Electrical and Computer Systems Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Research

3 Citations (Scopus)

Abstract

In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2^p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

Original language	English
Title of host publication	Proceedings - 2017 12th IEEE International Conference on ASIC
Editors	Yajie Qin, Zhiliang Hong, Ting-Ao Tang
Place of Publication	Piscataway NJ USA
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	1077-1080
Number of pages	4
ISBN (Electronic)	9781509066254, 9781509066230
ISBN (Print)	9781509066247, 9781509066261
DOIs	https://doi.org/10.1109/ASICON.2017.8252666
Publication status	Published - 2017
Event	IEEE International Conference on Advanced Semiconductor Integrated Circuits 2017 - Guiyang, China Duration: 25 Oct 2017 → 28 Oct 2017 Conference number: 12th

Conference

Conference	IEEE International Conference on Advanced Semiconductor Integrated Circuits 2017
Abbreviated title	ASICON 2017
Country/Territory	China
City	Guiyang
Period	25/10/17 → 28/10/17

Keywords

Folding technique
K-level decomposition
Polar code
SC decoder
VLSI implementation

Access to Document

10.1109/ASICON.2017.8252666

Cite this

Liang, X., She, Y., Vangala, H., You, X., Zhang, C., & Viterbo, E. (2017). An efficient successive cancellation polar decoder based on new folding approaches. In Y. Qin, Z. Hong, & T.-A. Tang (Eds.), Proceedings - 2017 12th IEEE International Conference on ASIC (pp. 1077-1080). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ASICON.2017.8252666

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title = "An efficient successive cancellation polar decoder based on new folding approaches",

abstract = "In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3\% and 39.1\% ALMs, compared to the non-decomposed SC decoder.",

keywords = "Folding technique, K-level decomposition, Polar code, SC decoder, VLSI implementation",

author = "Xiao Liang and Yechao She and Harish Vangala and Xiaohu You and Chuan Zhang and Emanuele Viterbo",

year = "2017",

doi = "10.1109/ASICON.2017.8252666",

language = "English",

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pages = "1077--1080",

editor = "Yajie Qin and Zhiliang Hong and Ting-Ao Tang",

booktitle = "Proceedings - 2017 12th IEEE International Conference on ASIC",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States of America",

note = "IEEE International Conference on Advanced Semiconductor Integrated Circuits 2017, ASICON 2017 ; Conference date: 25-10-2017 Through 28-10-2017",

}

Liang, X, She, Y, Vangala, H, You, X, Zhang, C & Viterbo, E 2017, An efficient successive cancellation polar decoder based on new folding approaches. in Y Qin, Z Hong & T-A Tang (eds), Proceedings - 2017 12th IEEE International Conference on ASIC. IEEE, Institute of Electrical and Electronics Engineers, Piscataway NJ USA, pp. 1077-1080, IEEE International Conference on Advanced Semiconductor Integrated Circuits 2017, Guiyang, China, 25/10/17. https://doi.org/10.1109/ASICON.2017.8252666

An efficient successive cancellation polar decoder based on new folding approaches. / Liang, Xiao; She, Yechao; Vangala, Harish et al.
Proceedings - 2017 12th IEEE International Conference on ASIC. ed. / Yajie Qin; Zhiliang Hong; Ting-Ao Tang. Piscataway NJ USA: IEEE, Institute of Electrical and Electronics Engineers, 2017. p. 1077-1080.

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Research

TY - GEN

T1 - An efficient successive cancellation polar decoder based on new folding approaches

AU - Liang, Xiao

AU - She, Yechao

AU - Vangala, Harish

AU - You, Xiaohu

AU - Zhang, Chuan

AU - Viterbo, Emanuele

N1 - Conference code: 12th

PY - 2017

Y1 - 2017

N2 - In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

AB - In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

KW - Folding technique

KW - K-level decomposition

KW - Polar code

KW - SC decoder

KW - VLSI implementation

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SN - 9781509066261

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CY - Piscataway NJ USA

T2 - IEEE International Conference on Advanced Semiconductor Integrated Circuits 2017

Y2 - 25 October 2017 through 28 October 2017

ER -

An efficient successive cancellation polar decoder based on new folding approaches

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