An efficient successive cancellation polar decoder based on new folding approaches

Xiao Liang, Yechao She, Harish Vangala, Xiaohu You, Chuan Zhang, Emanuele Viterbo

Research output: Chapter in Book/Report/Conference proceedingConference PaperOther

Abstract

In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
EditorsYajie Qin, Ting-Ao Tang, Zhiliang Hong
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages1077-1080
Number of pages4
Volume2017-October
ISBN (Electronic)9781509066247
DOIs
Publication statusPublished - 8 Jan 2018
EventIEEE International Conference on Advanced Semiconductor Integrated Circuits 2017 - Guiyang, China
Duration: 25 Oct 201728 Oct 2017
Conference number: 12th

Conference

ConferenceIEEE International Conference on Advanced Semiconductor Integrated Circuits 2017
Abbreviated titleASICON 2017
CountryChina
CityGuiyang
Period25/10/1728/10/17

Keywords

  • Folding technique
  • K-level decomposition
  • Polar code
  • SC decoder
  • VLSI implementation

Cite this

Liang, X., She, Y., Vangala, H., You, X., Zhang, C., & Viterbo, E. (2018). An efficient successive cancellation polar decoder based on new folding approaches. In Y. Qin, T-A. Tang, & Z. Hong (Eds.), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (Vol. 2017-October, pp. 1077-1080). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ASICON.2017.8252666
Liang, Xiao ; She, Yechao ; Vangala, Harish ; You, Xiaohu ; Zhang, Chuan ; Viterbo, Emanuele. / An efficient successive cancellation polar decoder based on new folding approaches. Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. editor / Yajie Qin ; Ting-Ao Tang ; Zhiliang Hong. Vol. 2017-October IEEE, Institute of Electrical and Electronics Engineers, 2018. pp. 1077-1080
@inproceedings{db0c568a442946299c28d1eb6944fc4f,
title = "An efficient successive cancellation polar decoder based on new folding approaches",
abstract = "In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3{\%} and 39.1{\%} ALMs, compared to the non-decomposed SC decoder.",
keywords = "Folding technique, K-level decomposition, Polar code, SC decoder, VLSI implementation",
author = "Xiao Liang and Yechao She and Harish Vangala and Xiaohu You and Chuan Zhang and Emanuele Viterbo",
year = "2018",
month = "1",
day = "8",
doi = "10.1109/ASICON.2017.8252666",
language = "English",
volume = "2017-October",
pages = "1077--1080",
editor = "Yajie Qin and Ting-Ao Tang and Zhiliang Hong",
booktitle = "Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017",
publisher = "IEEE, Institute of Electrical and Electronics Engineers",
address = "United States of America",

}

Liang, X, She, Y, Vangala, H, You, X, Zhang, C & Viterbo, E 2018, An efficient successive cancellation polar decoder based on new folding approaches. in Y Qin, T-A Tang & Z Hong (eds), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. vol. 2017-October, IEEE, Institute of Electrical and Electronics Engineers, pp. 1077-1080, IEEE International Conference on Advanced Semiconductor Integrated Circuits 2017, Guiyang, China, 25/10/17. https://doi.org/10.1109/ASICON.2017.8252666

An efficient successive cancellation polar decoder based on new folding approaches. / Liang, Xiao; She, Yechao; Vangala, Harish; You, Xiaohu; Zhang, Chuan; Viterbo, Emanuele.

Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. ed. / Yajie Qin; Ting-Ao Tang; Zhiliang Hong. Vol. 2017-October IEEE, Institute of Electrical and Electronics Engineers, 2018. p. 1077-1080.

Research output: Chapter in Book/Report/Conference proceedingConference PaperOther

TY - GEN

T1 - An efficient successive cancellation polar decoder based on new folding approaches

AU - Liang, Xiao

AU - She, Yechao

AU - Vangala, Harish

AU - You, Xiaohu

AU - Zhang, Chuan

AU - Viterbo, Emanuele

PY - 2018/1/8

Y1 - 2018/1/8

N2 - In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

AB - In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

KW - Folding technique

KW - K-level decomposition

KW - Polar code

KW - SC decoder

KW - VLSI implementation

UR - http://www.scopus.com/inward/record.url?scp=85044774046&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2017.8252666

DO - 10.1109/ASICON.2017.8252666

M3 - Conference Paper

VL - 2017-October

SP - 1077

EP - 1080

BT - Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017

A2 - Qin, Yajie

A2 - Tang, Ting-Ao

A2 - Hong, Zhiliang

PB - IEEE, Institute of Electrical and Electronics Engineers

ER -

Liang X, She Y, Vangala H, You X, Zhang C, Viterbo E. An efficient successive cancellation polar decoder based on new folding approaches. In Qin Y, Tang T-A, Hong Z, editors, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October. IEEE, Institute of Electrical and Electronics Engineers. 2018. p. 1077-1080 https://doi.org/10.1109/ASICON.2017.8252666