An efficient successive cancellation polar decoder based on new folding approaches

Xiao Liang, Yechao She, Harish Vangala, Xiaohu You, Chuan Zhang, Emanuele Viterbo

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearch

3 Citations (Scopus)

Abstract

In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.

Original languageEnglish
Title of host publicationProceedings - 2017 12th IEEE International Conference on ASIC
EditorsYajie Qin, Zhiliang Hong, Ting-Ao Tang
Place of PublicationPiscataway NJ USA
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages1077-1080
Number of pages4
ISBN (Electronic)9781509066254, 9781509066230
ISBN (Print)9781509066247, 9781509066261
DOIs
Publication statusPublished - 2017
EventIEEE International Conference on Advanced Semiconductor Integrated Circuits 2017 - Guiyang, China
Duration: 25 Oct 201728 Oct 2017
Conference number: 12th

Conference

ConferenceIEEE International Conference on Advanced Semiconductor Integrated Circuits 2017
Abbreviated titleASICON 2017
Country/TerritoryChina
CityGuiyang
Period25/10/1728/10/17

Keywords

  • Folding technique
  • K-level decomposition
  • Polar code
  • SC decoder
  • VLSI implementation

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