A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS

Daniel Morrison, Simon Kennedy, Dennis Delic, Mehmet Yuce, Jean-Michel Redoute

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearchpeer-review

1 Citation (Scopus)

Abstract

This paper presents a triple integration time-to-amplitude conversion (TAC) scheme for high resolution SPAD time of flight cameras. Two reference integrators are added to the conventional integration based TAC design, allowing the scheme to be resistant to PVT variation, common mode noise and capacitive discharge. An implementation in 130 nm CMOS is presented with experimental validation to show a significant improvement over the traditional single integration scheme. The measured performance shows that the triple integration interpolator has an INL, DNL and RMS jitter of 85.1 ps, 43 ps and 65 ps respectively.

Original languageEnglish
Title of host publication2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS)
EditorsElena Blokhina, Francois Rivet
Place of PublicationPiscataway NJ USA
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages13-16
Number of pages4
ISBN (Electronic)9781538695623
ISBN (Print)9781538691168
DOIs
Publication statusPublished - 2018
EventIEEE International Conference on Electronics, Circuits and Systems 2018 - Bordeaux, France
Duration: 9 Dec 201812 Dec 2018
Conference number: 25th

Conference

ConferenceIEEE International Conference on Electronics, Circuits and Systems 2018
Abbreviated titleICECS 2018
CountryFrance
CityBordeaux
Period9/12/1812/12/18

Keywords

  • Single Photon Avalanche Diode (SPAD)
  • Time-of-Flight (ToF)
  • Time-to-Amplitude Conversion (TAC)
  • Timing

Cite this

Morrison, D., Kennedy, S., Delic, D., Yuce, M., & Redoute, J-M. (2018). A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS. In E. Blokhina, & F. Rivet (Eds.), 2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS) (pp. 13-16). Piscataway NJ USA: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICECS.2018.8617939
Morrison, Daniel ; Kennedy, Simon ; Delic, Dennis ; Yuce, Mehmet ; Redoute, Jean-Michel. / A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS. 2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). editor / Elena Blokhina ; Francois Rivet. Piscataway NJ USA : IEEE, Institute of Electrical and Electronics Engineers, 2018. pp. 13-16
@inproceedings{efe323f977ba4f1bab7bf431f2e34cb4,
title = "A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS",
abstract = "This paper presents a triple integration time-to-amplitude conversion (TAC) scheme for high resolution SPAD time of flight cameras. Two reference integrators are added to the conventional integration based TAC design, allowing the scheme to be resistant to PVT variation, common mode noise and capacitive discharge. An implementation in 130 nm CMOS is presented with experimental validation to show a significant improvement over the traditional single integration scheme. The measured performance shows that the triple integration interpolator has an INL, DNL and RMS jitter of 85.1 ps, 43 ps and 65 ps respectively.",
keywords = "Single Photon Avalanche Diode (SPAD), Time-of-Flight (ToF), Time-to-Amplitude Conversion (TAC), Timing",
author = "Daniel Morrison and Simon Kennedy and Dennis Delic and Mehmet Yuce and Jean-Michel Redoute",
year = "2018",
doi = "10.1109/ICECS.2018.8617939",
language = "English",
isbn = "9781538691168",
pages = "13--16",
editor = "Elena Blokhina and Francois Rivet",
booktitle = "2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS)",
publisher = "IEEE, Institute of Electrical and Electronics Engineers",
address = "United States of America",

}

Morrison, D, Kennedy, S, Delic, D, Yuce, M & Redoute, J-M 2018, A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS. in E Blokhina & F Rivet (eds), 2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). IEEE, Institute of Electrical and Electronics Engineers, Piscataway NJ USA, pp. 13-16, IEEE International Conference on Electronics, Circuits and Systems 2018, Bordeaux, France, 9/12/18. https://doi.org/10.1109/ICECS.2018.8617939

A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS. / Morrison, Daniel; Kennedy, Simon; Delic, Dennis; Yuce, Mehmet; Redoute, Jean-Michel.

2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). ed. / Elena Blokhina; Francois Rivet. Piscataway NJ USA : IEEE, Institute of Electrical and Electronics Engineers, 2018. p. 13-16.

Research output: Chapter in Book/Report/Conference proceedingConference PaperResearchpeer-review

TY - GEN

T1 - A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS

AU - Morrison, Daniel

AU - Kennedy, Simon

AU - Delic, Dennis

AU - Yuce, Mehmet

AU - Redoute, Jean-Michel

PY - 2018

Y1 - 2018

N2 - This paper presents a triple integration time-to-amplitude conversion (TAC) scheme for high resolution SPAD time of flight cameras. Two reference integrators are added to the conventional integration based TAC design, allowing the scheme to be resistant to PVT variation, common mode noise and capacitive discharge. An implementation in 130 nm CMOS is presented with experimental validation to show a significant improvement over the traditional single integration scheme. The measured performance shows that the triple integration interpolator has an INL, DNL and RMS jitter of 85.1 ps, 43 ps and 65 ps respectively.

AB - This paper presents a triple integration time-to-amplitude conversion (TAC) scheme for high resolution SPAD time of flight cameras. Two reference integrators are added to the conventional integration based TAC design, allowing the scheme to be resistant to PVT variation, common mode noise and capacitive discharge. An implementation in 130 nm CMOS is presented with experimental validation to show a significant improvement over the traditional single integration scheme. The measured performance shows that the triple integration interpolator has an INL, DNL and RMS jitter of 85.1 ps, 43 ps and 65 ps respectively.

KW - Single Photon Avalanche Diode (SPAD)

KW - Time-of-Flight (ToF)

KW - Time-to-Amplitude Conversion (TAC)

KW - Timing

UR - http://www.scopus.com/inward/record.url?scp=85062288375&partnerID=8YFLogxK

U2 - 10.1109/ICECS.2018.8617939

DO - 10.1109/ICECS.2018.8617939

M3 - Conference Paper

SN - 9781538691168

SP - 13

EP - 16

BT - 2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS)

A2 - Blokhina, Elena

A2 - Rivet, Francois

PB - IEEE, Institute of Electrical and Electronics Engineers

CY - Piscataway NJ USA

ER -

Morrison D, Kennedy S, Delic D, Yuce M, Redoute J-M. A triple integration timing scheme for SPAD time of flight imaging sensors in 130 nm CMOS. In Blokhina E, Rivet F, editors, 2018 25th IEEE International Conference on Electronics Circuits and Systems (ICECS). Piscataway NJ USA: IEEE, Institute of Electrical and Electronics Engineers. 2018. p. 13-16 https://doi.org/10.1109/ICECS.2018.8617939