A basic data routing model for a coarse-grain reconfigurable hardware

Jie Guo, Gleb Belov, Gerhard P. Fettweis

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Abstract

Synchronous Transfer Architecture (STA) is a coarse-grain reconfigurable hardware. It is modelled by using a common machine description that is suitable for both compiler and core generator. STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for such ISA needs highly optimizing techniques. This paper presents a basic data routing Integer Linear Programming (ILP) model for STA code generation. We will also show in this paper, the execution time of the assembly code can be dramatically reduced. The code generation can be accomplished in acceptable time and it can even be real time by reducing the degree of optimality.

Original languageEnglish
Title of host publicationReconfigurable Computing
Subtitle of host publicationArchitectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers
PublisherSpringer-Verlag London Ltd.
Pages419-424
Number of pages6
ISBN (Print)9783540367086
Publication statusPublished - 1 Jan 2006
Event2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 - Delft, United States of America
Duration: 1 Mar 20063 Mar 2006

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3985 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference2nd International Workshop on Applied Reconfigurable Computing, ARC 2006
CountryUnited States of America
CityDelft
Period1/03/063/03/06

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