A basic data routing model for a coarse-grain reconfigurable hardware

Jie Guo; Gleb Belov; Gerhard P. Fettweis

A basic data routing model for a coarse-grain reconfigurable hardware

Jie Guo, Gleb Belov, Gerhard P. Fettweis

Department of Data Science & AI

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Research › peer-review

Abstract

Synchronous Transfer Architecture (STA) is a coarse-grain reconfigurable hardware. It is modelled by using a common machine description that is suitable for both compiler and core generator. STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for such ISA needs highly optimizing techniques. This paper presents a basic data routing Integer Linear Programming (ILP) model for STA code generation. We will also show in this paper, the execution time of the assembly code can be dramatically reduced. The code generation can be accomplished in acceptable time and it can even be real time by reducing the degree of optimality.

Original language	English
Title of host publication	Reconfigurable Computing
Subtitle of host publication	Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers
Publisher	Springer-Verlag London Ltd.
Pages	419-424
Number of pages	6
ISBN (Print)	9783540367086
Publication status	Published - 1 Jan 2006
Event	2nd International Workshop on Applied Reconfigurable Computing, ARC 2006 - Delft, United States of America Duration: 1 Mar 2006 → 3 Mar 2006

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	3985 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	2nd International Workshop on Applied Reconfigurable Computing, ARC 2006
Country/Territory	United States of America
City	Delft
Period	1/03/06 → 3/03/06

Cite this

Guo, J., Belov, G., & Fettweis, G. P. (2006). A basic data routing model for a coarse-grain reconfigurable hardware. In Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers (pp. 419-424). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3985 LNCS). Springer-Verlag London Ltd..

Guo, Jie ; Belov, Gleb ; Fettweis, Gerhard P. / A basic data routing model for a coarse-grain reconfigurable hardware. Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer-Verlag London Ltd., 2006. pp. 419-424 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "Synchronous Transfer Architecture (STA) is a coarse-grain reconfigurable hardware. It is modelled by using a common machine description that is suitable for both compiler and core generator. STA is a Very Long Instruction Word (VLIW) architecture and in addition it uses a non-orthogonal Instruction Set Architecture (ISA). Generating efficient code for such ISA needs highly optimizing techniques. This paper presents a basic data routing Integer Linear Programming (ILP) model for STA code generation. We will also show in this paper, the execution time of the assembly code can be dramatically reduced. The code generation can be accomplished in acceptable time and it can even be real time by reducing the degree of optimality.",

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Guo, J, Belov, G & Fettweis, GP 2006, A basic data routing model for a coarse-grain reconfigurable hardware. in Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3985 LNCS, Springer-Verlag London Ltd., pp. 419-424, 2nd International Workshop on Applied Reconfigurable Computing, ARC 2006, Delft, United States of America, 1/03/06.

A basic data routing model for a coarse-grain reconfigurable hardware. / Guo, Jie; Belov, Gleb; Fettweis, Gerhard P.

Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer-Verlag London Ltd., 2006. p. 419-424 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3985 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference Paper › Research › peer-review

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Guo J, Belov G, Fettweis GP. A basic data routing model for a coarse-grain reconfigurable hardware. In Reconfigurable Computing: Architectures and Applications - Second International Workshop, ARC 2006, Revised Selected Papers. Springer-Verlag London Ltd. 2006. p. 419-424. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

A basic data routing model for a coarse-grain reconfigurable hardware

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